Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effects

ABSTRACT

Techniques for modeling delay and transition times of logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

The present Application is a Division of U.S. patent application Ser.No. 10/366,439 filed on Feb. 13, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is related to circuit modeling methods andsoftware, and more particularly to logic circuit modeling methods andsoftware that compute loading effects on logical circuit block signalperformance.

2. Description of Related Art

Circuit modeling methods, typically implemented in software tools thatsimulate the performance of circuits for design verification provide amechanism for optimizing and ensuring proper performance of IntegratedCircuits (IC) including Very-Large-Scale Integrated (VLSI) circuits.Logical circuits are typically represented as circuit blocks having amodeled response to input state changes. In response to an input change,a delay time and a transition time are generally used to generate theoutput voltage of the logical circuit block within the model.

The transition time and delay time of a logical circuit block vary overvarious parameters of the circuit block, such as output transistor size,power supply voltage and temperature. The transition time and delay timemay also be modeled in terms of input voltage swing and transition time.Existing models take all or some of the above factors into account inorder to determine the output signal produced by a logical circuitblock.

Additionally, output loading characteristics have a large effect on theoutput signal and various techniques have been developed within presentcircuit models and modeling software to take loading effects intoaccount. The simplest model used in present simulation tools is a lumpedcapacitance coupled to the output of the logical circuit block. Thelumped capacitance represents all of the loading capacitance connectedto the output of the logical circuit block, and may in the simplest casebe equal to all of the capacitance connected to the logical circuitblock output, or may be a capacitance value determined by sophisticatedmodels of the interconnect resistance and capacitances at various pointsin the circuits connected to the output of the logical circuit block.

The above-referenced patent application describes a pi-network modelthat includes two capacitors determined from distributed capacitancesconnected to the output of a logical circuit block, along with theeffects of the wire resistances connecting the capacitances. Thepi-network model provides an improved calculation of the effects ofdistributed capacitances connected to the output of the logical circuitblock.

However, present circuit models have progressively reduced accuracy asthe logical circuit block output loading capacitance becomes dominatedby transistor gate capacitances. Since the load on the output of alogical circuit block is typically at least one logical gate inputconnected via a typically low-resistance interconnect, the transistorgate capacitance, which is not in actuality a linear capacitance but anon-linear capacitance that varies with output signal voltage, has asignificant impact on the logical circuit block transition time anddelay time. The non-linear nature of the loading gate capacitancescauses the transition time and delay time to diverge from valuespredicted by a simple capacitive model, making a simple shuntcapacitance load model or fixed capacitive network load modelineffective for predicting both the transition time and delay time of alogical circuit block.

However, modeling gate capacitance loading effects on a circuit outputis a complicated simulation task, as logical circuit block performancemust be modeled over the complete range of device sizes that areencountered in actual designs. Transistor device size (and hence gatecapacitance) is typically a static value in designs simulated by circuitsimulation tools such as SPICE.

Therefore, it would be desirable to provide modeling methods andmodeling software that accurately predict the performance of a logicalcircuit block as the logical circuit block output load varies betweenpredominantly transistor gate capacitance and predominantly wirecapacitance. It would further be desirable to predict non-linear effectsof logical circuit block loading on logical circuit block transitiontime and delay time. It would further be desirable to provide a methodfor determining characteristics of the logical circuit block withouthaving to model the logical circuit block over loading circuittransistor device size changes.

SUMMARY OF THE INVENTION

The above objectives of accurately predicting the performance of alogical circuit block as the logical circuit block output load variesbetween predominantly transistor gate capacitance and predominantly wirecapacitance and predicting non-linear effects of logical circuit blockloading on logical circuit block transition time and delay time areaccomplished in a method for modeling logical circuit block behavior.

The method may be embodied in a computer system executing programinstructions for carrying out the steps of the method and may further beembodied in a computer program product containing program instructionsin computer-readable form for carrying out the steps of the method.

The method computes a transition time of a logical circuit block outputas a first mathematical function of transistor gate capacitanceconnected to the output of the logical circuit block and a delay time asa second mathematical function of the transistor gate capacitance. Thefirst and second functions may also include dependence on N-channel andP-channel gate capacitances separately or dependence on a N-channel toP-channel capacitance ratio. The first and second functions also includedependence on a “static capacitance”, a term used here to represent wireand pin capacitances, etc. that are linear, separate from the transistorgate capacitance.

The method also includes a technique for determining the effects of gatecapacitance loading on transition times and delay times to determinecoefficients of the first and second mathematical functions above. Alogical circuit block output including loading transistor(s) and avariable static capacitance are simulated using a circuit simulationtool such as SPICE. A current controlled current source is used to shuntoutput current in response to a measured current entering the loadingtransistor(s), providing a means for changing the apparent size of (oreffectively removing) the transistors from the model without changingtransistor device sizes.

The foregoing and other objectives, features, and advantages of theinvention will be apparent from the following, more particular,description of the preferred embodiment of the invention, as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial diagram of a workstation computer system in whichmethods in accordance with an embodiment of the present invention areperformed.

FIG. 2 is a schematic diagram of a portion of a logical integratedcircuit model in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram of a measurement circuit that can be usedto determine characteristics of a circuit model in accordance with anembodiment of the present invention.

FIG. 4 is a flow chart of a method in accordance with an embodiment ofthe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Referring to the figures, and particularly to FIG. 1, a workstationcomputer system, in which methods according to an embodiment of thepresent invention are performed, is depicted. A workstation computer 12,having a processor 16 coupled to a memory 17, for executing programinstructions from memory 17, wherein the program instructions includeprogram instructions for executing one or more methods in accordancewith an embodiment of the present invention.

Workstation computer 12 is coupled to a graphical display 13 fordisplaying program output such as simulation results and circuitstructure input and verification programs implementing embodiments ofthe present invention. Workstation computer 12 is further coupled toinput devices such as a mouse 15 and a keyboard 14 for receiving userinput. Workstation computer may be coupled to a public network such asthe Internet, or may be coupled to a private network such as the various“intra-nets”, or may not be connected to any network at all, andsoftware containing program instructions embodying methods in accordancewith embodiments of the present invention may be located on remotecomputers or locally within workstation computer 12.

Referring now to FIG. 2, a portion of an integrated circuit is depictedto illustrate a model in accordance with an embodiment of the presentinvention. Logic block L1 is simulated to produce an output voltagewaveform V_(o) (shown in balloon 11), calculated according to theillustrated model as a response to input voltage waveform V_(i) (shownin balloon 10). The illustrated model uses a delay time T_(d) andtransition time T_(r) to determine a linear voltage response to V_(i).The 50% voltage point of output signal V_(o) is set at interval T_(d)after the 50% voltage point of input signal V_(i) and the transitiontime T_(r) determines the slope of output voltage waveform V_(o). Whilethis linear waveform model is of a type in common use and is sufficientto illustrate the techniques of the present invention, the model of thepresent invention may be used with other types of waveform modelingincluding higher-order waveshape models or piecewise linear models thatcompute an output waveform using calculations performed on sampled inputvoltage waveform points.

All of the illustrations and formulations in the following descriptionare directed toward a rising transition time and a delay time. Actualmodels will generally include separate falling transition times and mayinclude two or more delay times—for falling edges, rising edges and thevarious transfer functions of the circuit. The model of the presentinvention is equally applicable to rising transition time and fallingtransition time modeling either separately computed or provided by oneformula and it should be understood that they can be usedinterchangeably with respect to the discussion hereinafter, exceptingthe actions of transistors described with respect to a particular signaledge, etc.

The model of the present invention provides the mathematical functionsthat calculate T_(r) and T_(d) in conformity with a multitude of circuitvariables. Generally the mathematical functions employed to computeT_(r) and T_(d) are functions of input voltage swing and slew rate,power supply voltages, temperature, device sizes and types. The modelalso includes response to various and varying load conditions and thepresent invention concerns the accurate modeling of load response byincluding a model of response to non-linear capacitance provided bygates of transistors (N2,P2,N3,P3) that are connected to the logicalcircuit block (L1) output being modeled. The input capacitance of a MOStransistor increases as the channel widens, so that the total inputcapacitance of a logical gate is a complex function of the gate voltageand depends on both devices (for a CMOS input such as those illustratedby logical circuit blocks L2 and L3). The separate consideration ofcircuit response to static capacitance C_(S) and transistor gatecapacitance provides a more accurate model than previously used modelsthat produce a response only to static capacitance.

Typically, prior art models include a response only to staticcapacitance which may be the total of all load capacitance or aneffective capacitance from a network that takes into account wiringresistance, such as the pi-network model described in theabove-referenced patent application. The techniques of the presentinvention may also be used with network models, but the illustrationprovided herein is one in which the transition time and delay time of alogical circuit block is modeled directly from input variables thatignore resistance and consider only the totals of the variouscapacitances.

One model in accordance with the present invention models the responseof the circuit to N-channel device gate capacitance and a separateresponse to P-channel device gate capacitance. These capacitances mightbe obtained by totaling all of the gate capacitances of the N-channeldevices (N2 and N3) in the connected inputs of logical circuit blocks L2and L3 to generate a total NFET gate capacitance C_(N) and all of thegate capacitances of the P-channel devices (P2 and P3) in the connectedinputs of logical circuit blocks L2 and L3 to generate a total NFET gatecapacitance Cp. The illustration depicts two inputs connected to theoutput of circuit block L1, but a circuit may be loaded by any number ofconnected circuit inputs and is also not restricted to a particularconfiguration of circuit inputs. For example, an NMOS circuit (asopposed to the depicted CMOS circuit) would include a single N-channelgate connection per input.

The model also includes a response to the total of all static shuntcapacitance C_(S) not due to the input gate capacitances of logicalcircuit blocks L2 and L3, such as output capacitances, wire capacitancesand other interconnect capacitances. The representative staticcapacitance is included in the transition time and delay time modelalong with, but separate from the transistor gate capacitances. Theresult is that the dependence of the capacitive effect of the gateconnections can be modeled more accurately for: the two different edgesof signal transition, the device temperatures and other factors.

The model is generated by measuring (or simulating using precise analogsimulation tools) logical circuit block L1 output behavior (transitiontime and delay time) at various sampling points of the input variables(temperature, input slew rate, power supply voltage, static loadcapacitance, N-channel device transistor load capacitance, P-channeltransistor gate load capacitance (or combined gate-load capacitance),etc.) and curve-fitting the transition time and delay time equations tothe measured data, or generating a lookup-table model of the measureddata.

The transition time and delay time equations may be expressed asfollows:

T _(r) =f1(C _(S) , C _(N) , C _(P), . . . )

T _(d) =f2(C _(S) , C _(N) , C _(P), . . . )

Where C_(S)=total of all static capacitances connected to the output oflogical circuit block L1, C_(N)=total of all N-channel inputcapacitances connected, and C_(P)=total of all P-channel inputcapacitances connected. The totals may also be adjusted; for example,the P-channel and N-channel totals may be reduced to take into accountwire resistance R_(W) or other effects, and the static capacitance mayalso be adjusted as well. The primary feature of the models of thepresent invention is the separate treatment of transistor gatecapacitance.

An alternative model expresses the transition time and delay time interms of the ratio of N-channel to P-channel transistor gatecapacitances:

T _(r) =f3(C _(S) , C _(T) , R _(N/P), . . . )

T _(d) =f4(C _(S) , C _(T) , R _(N/P), . . . )

Where C_(T) may be either of the gate capacitances or their sum andR_(N/P)=C_(N)/C_(P).

Another alternative is to express the transistor gate capacitance as afraction (or a separate fraction for N-channel and P-channel devices) ofthe static capacitance, yielding:

T _(r) =f5(C _(S) , R _(T/S), . . . )

T _(d) =f6(C _(S) , R _(T/S), . . . )

Where R_(T/S) is the ratio of the transistor gate capacitances to thestatic capacitances, or

T _(r) =f7(C _(S) , R _(N/S) , R _(P/S) . . . )

T _(d) =f8(C _(S) , R _(N/S) , R _(P/S), . . . )

Where R_(N/S) and R_(P/S) are the ratios of the individual (N or P)transistor gate capacitances to the static capacitances, respectively.

In essence, all of the above models are equivalent to either the modeltreating N and P channel devices together (as one lumped transistor gatecapacitance) or the model that treats them separately. The exemplarymodels presented above represent a reformulation of the delay time andtransition time model in various combinations depending on desired inputvariables. While they are illustrative of the method of the presentinvention, they are not intended to be exhaustive or otherwise limiting.

Referring now to FIG. 3, a circuit that may be used in an analogsimulator or for other measurement purposes to determine thecharacteristics of the model for transition time and delay time isshown. A circuit simulator such as SPICE may be used to simulate thecircuit of FIG. 3, in order to determine the transition time and delaytime functions of logical circuit block L1. Loading transistors Nx andPx have a channel width set to a convenient value of “gate capacitance”and capacitance C_(X) is set to represent a typical load at the outputof transistors Nx and Px. Variable capacitor VC1 represents the staticcapacitance C_(S) and can be set to different values including zero tosimulate variation over the wire capacitance variable in the logicalcircuit models. A current meter (I_(P),I_(N)) is inserted into eachtransistor gate circuit. The current meters can then control currentdependent shunt current source IdIs, which is used to multiply the gatecurrent of the transistors in order to simulate varying the individualgate capacitances of each transistor type (N or P channel). If shuntcurrent IdIs is set to a value of −1*(I_(P)+I_(N)), the transistors areeffectively removed leaving only capacitor VC1. If the capacitance ofcapacitor VC1 is set to zero, and shunt current IdIs is set to a valueof −1*(I_(P)−I_(N)), then a measurement can be taken for zero wirecapacitance and, C_(P)=0 and C_(N)=2*NFET capacitance. In general, ifshunt current IdIs is set to a value of (k_(P)I_(P)+k_(N)I_(N)), wherek_(P), k_(N) are variable coefficients, then the P-channel transistorgate capacitance is effectively multiplied by (1+k_(P)) and theN-channel transistor gate capacitance is effectively multiplied by(1+k_(N)), and k_(P) and k_(N) can be swept independently over a rangeof interest without having to modify the model.

Referring now to FIG. 4, a method in accordance with an embodiment ofthe present invention is depicted in a flowchart. Timing analysisgenerates an input waveform for a logic transition at an input of afirst logical circuit block. The input waveform (which may be just the50% voltage time point) is received by the method (step 30). Next, themethod calculates the transition time and delay time of the firstlogical circuit block output as a function of circuit variables and loadvariables, where the load variables include a static connectedcapacitance value and at least one transistor gate capacitance valuerepresenting transistors in the input stage of a second logical circuitblock connected to the output of the first logical circuit block (step32). Finally, an output voltage waveform of the first logical circuitblock is generated from the transition time and delay time of the firstlogical circuit block and the input waveform (step 34).

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in form,and details may be made therein without departing from the spirit andscope of the invention.

1. A method for modeling, in a computer system, the behavior of alogical circuit block, the method comprising: first calculating in saidcomputer system a transition time of said logical circuit block as afirst mathematical function of a transistor gate capacitance of one ormore logical circuit inputs connected to an output of said logicalcircuit block and a static load capacitance value, wherein said firstmathematical function is separately dependent on said transistor gatecapacitance and said static load capacitance value; second calculatingin said computer system a delay time of said logical circuit block as asecond mathematical function of said transistor gate capacitance andsaid static load capacitance value, wherein said second mathematicalfunction is separately dependent on said transistor gate capacitance andsaid static load capacitance value, and wherein coefficients of saidfirst and second mathematical functions with respect to said transistorgate capacitance are determined in conformity with a variation of saidtransistor gate capacitance with respect to transistor gate voltage; anddisplaying by said computer system, a result of at least one of saidfirst and second calculating.
 2. The method of claim 1, wherein saidfirst and second mathematical functions are functions of a totalcapacitance and a ratio of said transistor gate capacitance to a totalcapacitance connected to said output of said logical circuit block, andwherein said method further comprises: first computing said transistorgate capacitance by multiplying said total capacitance by said ratio;and second computing said static capacitance by subtracting saidtransistor gate capacitance from said total capacitance.
 3. The methodof claim 1, further comprising: first computing a first capacitance formodeling one or more N-channel devices connected to said output of saidlogical circuit block; second computing a second capacitance formodeling one or more P-channel devices connected to said output of saidlogical circuit block, and wherein said first and second mathematicalfunctions are further functions of said first and second capacitances,whereby loading effects of said N-channel and P-channel devices areseparately accounted for in said first and second calculating.
 4. Themethod of claim 3, further comprising: first totaling a first pluralityof gate capacitances of said N-channel devices to determine said firstcapacitance; and second totaling a second plurality of gate capacitancesof said P-channel devices to determine said first capacitance.
 5. Themethod of claim 1, wherein said first and second mathematical functionsare further functions of a ratio of a first capacitance of one or moreN-channel devices connected to said output of said logical circuit blockand a second capacitance of one or more P-channel devices connected tosaid output of said logical circuit block.
 6. A workstation computersystem including a memory for storing program instructions and data, anda processor for executing said program instructions, and wherein saidprogram instructions comprise program instructions for: firstcalculating a transition time of said logical circuit block as a firstmathematical function of a transistor gate capacitance of one or morelogical circuit inputs connected to an output of said logical circuitblock and a static load capacitance value, wherein said firstmathematical function is separately dependent on said transistor gatecapacitance and said static load capacitance value, second calculatingdelay time of said logical circuit block as a second mathematicalfunction of said transistor gate capacitance and said static loadcapacitance value, wherein said second mathematical function isseparately dependent on said transistor gate capacitance and said staticload capacitance value, and wherein coefficients of said first andsecond mathematical functions with respect to said transistor gatecapacitance are determined in conformity with a variation of saidtransistor gate capacitance with respect to transistor gate voltage, anddisplaying a result of at least one of said first and secondcalculating.
 7. The workstation computer system of claim 6, wherein saidfirst and second mathematical functions are functions of a totalcapacitance and a ratio of said transistor gate capacitance to a totalcapacitance connected to said output of said logical circuit block, andwherein program instructions further comprise program instructions for:first computing said transistor gate capacitance by multiplying saidtotal capacitance by said ratio; and second computing said staticcapacitance by subtracting said transistor gate capacitance from saidtotal capacitance.
 8. The workstation computer system of claim 6,wherein said program instructions further comprise program instructionsfor: first computing a first capacitance for modeling one or moreN-channel devices connected to said output of said logical circuitblock; second computing a second capacitance for modeling one or moreP-channel devices connected to said output of said logical circuitblock, and wherein said first and second mathematical functions arefurther functions of said first and second capacitances, whereby loadingeffects of said N-channel and P-channel devices are separately accountedfor in said first and second calculating.
 9. The workstation computersystem of claim 8, wherein said program instructions further compriseprogram instructions for: first totaling a first plurality of gatecapacitances of said N-channel devices to determine said firstcapacitance; and second totaling a second plurality of gate capacitancesof said P-channel devices to determine said first capacitance.
 10. Theworkstation computer system of claim 6, wherein said first and secondmathematical functions are further functions of a ratio of a firstcapacitance of one or more N-channel devices connected to said output ofsaid logical circuit block and a second capacitance of one or moreP-channel devices connected to said output of said logical circuitblock.
 11. A computer program product comprising a computer-readablestorage medium encoding program instructions and data for execution on ageneral-purpose computer system, wherein said program instructionscomprise program instructions for: first calculating a transition timeof said logical circuit block as a first mathematical function of atransistor gate capacitance of one or more logical circuit inputsconnected to an output of said logical circuit block and a static loadcapacitance value, wherein said first mathematical function isseparately dependent on said transistor gate capacitance and said staticload capacitance value, second calculating delay time of said logicalcircuit block as a second mathematical function of said transistor gatecapacitance and said static load capacitance value, wherein said secondmathematical function is separately dependent on said transistor gatecapacitance and said static load capacitance value, and whereincoefficients of said first and second mathematical functions withrespect to said transistor gate capacitance are determined in conformitywith a variation of said transistor gate capacitance with respect totransistor gate voltage, and displaying a result of at least one of saidfirst and second calculating.
 12. The computer program product of claim11, wherein said first and second mathematical functions are functionsof a total capacitance and a ratio of said transistor gate capacitanceto a total capacitance connected to said output of said logical circuitblock, and wherein program instructions further comprise programinstructions for: first computing said transistor gate capacitance bymultiplying said total capacitance by said ratio; and second computingsaid static capacitance by subtracting said transistor gate capacitancefrom said total capacitance.
 13. The computer program product of claim11, wherein said program instructions further comprise programinstructions for: first computing a first capacitance for modeling oneor more N-channel devices connected to said output of said logicalcircuit block; second computing a second capacitance for modeling one ormore P-channel devices connected to said output of said logical circuitblock, and wherein said first and second mathematical functions arefurther functions of said first and second capacitances, whereby loadingeffects of said N-channel and P-channel devices are separately accountedfor in said first and second calculating.
 14. The computer programproduct of claim 13, wherein said program instructions further compriseprogram instructions for: first totaling a first plurality of gatecapacitances of said N-channel devices to determine said firstcapacitance; and second totaling a second plurality of gate capacitancesof said P-channel devices to determine said first capacitance.
 15. Thecomputer program product of claim 11, wherein said first and secondmathematical functions are further functions of a ratio of a firstcapacitance of one or more N-channel devices connected to said output ofsaid logical circuit block and a second capacitance of one or moreP-channel devices connected to said output of said logical circuitblock.